More DDR product information
The FAN5068 DDR memory regulator combines a high-efficiency PWM controller to generate the supply voltage, VDDQ, and a linear regulator to generate VTT, the termination voltage. Synchronous rectification provides high-efficiency over a wide range of load currents. Efficiency is further enhanced by using the low-side MOSFET's RDS(ON) to sense current instead of a series sense resistor.
In S3 mode, only the VDDQ switcher and the 3.3V regulators remain on while the VTT and ULDO regulators are shut off. To avoid "glitching" the VDDQ output during the transition from S3 to S0, the three linear regulators use the SS capacitor to limit their slew rates, thereby limiting the surge current from the VDDQ output. PGOOD becomes true in S0 only when all 3 regulators have achieved stable outputs.
In S5 (EN = 0), the 3.3V internal LDO stays on, while the other regulators are powered down.
The VDDQ PWM regulator is a sampled current mode control with external compensation to achieve fast load transient response and provide system design optimization.
The VTT regulator derives its reference and takes its power from the VDDQ PWM regulator output using a precision internal voltage divider to set its output at 1/2 of VDDQ. The VTT termination regulator is capable of sourcing or sinking at least 1.5A peak current.
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